XC4VSX35-12FFG668C

Product Summary

The XC4VSX35-12FFG668C is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or ASMBL column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families (platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of hard-IP core blocks completes the system solution. These cores include the PowerPC. processors (with a new APU interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. The XC4VSX35-12FFG668C is produced on a state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible features, The XC4VSX35-12FFG668C enhances programmable logic design capabilities and is a powerful alternative to ASIC technology.

Parametrics

XC4VSX35-12FFG668C absolute maximum ratings: (1)Package: 668FCBGA ; (2)Device Logic Units: 34560 ; (3)Typical Operating Supply Voltage: 1.2V ; (4)Maximum Number of User I/Os: 448 ; (5)RAM Bits: 3538944 ; (6)Operating Temperature: 0℃ to 85℃; (7)Speed Grade: 12.

Features

XC4VSX35-12FFG668C features: (1)Three families LX/SX/FX: Virtex-4 LX: High-performance logic applications solution, Virtex-4 FX: High-performance, full-featured solution for embedded platform applications, Virtex-4 SX: High-performance solution for Digital Signal Processing (DSP) applications; (2)Xesium Clock Technology: Digital Clock Manager (DCM) blocks, Additional Phase-Matched Clock Dividers (PMCD), Differential Global Clocks; (3)XtremeDSP Slice: 18×18, two’s complement, signed Multiplier, Optional pipeline stages, Built-In Accumulator (48-bits) & Adder/Subtracter; (4)Smart RAM Memory Hierarchy; (5)SelectIO Technology; (6)Flexible Logic Resources; (7)Built-in System Monitor (voltage/temp. measurement); (8)10-bit, 200kSPS A/D Converter (ADC); (9)Secure Chip AES Bitstream Encryption; (10)90-nm copper CMOS process; (11)1.2V core voltage; (12)Flip-Chip Packaging; (13)RocketIO?622 Mb/s to 11.1 Gb/s Multi-Gigabit Transceivers (MGT) (FX only); (14)Multiple Tri-Mode Ethernet MACs (FX only).

Diagrams