5962-8866206na

Product Summary

The 5962-8866206na is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The 5962-8866206na is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or high. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to improve alpha immunity.

Parametrics

Absolute maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage to Ground Potential (Pin 28 to Pin 14): –0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High Z State: –0.5V to VCC + 0.5V; (5)DC Input Voltage: –0.5V to VCC + 0.5V; (6)Output Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage: >2001V; (8)(per MIL-STD-883, Method 3015) Latch-Up Current: >200mA.

Features

Features: (1)High speed: 10 ns; (2)Fast tDOE; (3)CMOS for optimum speed/power; (4)Low active power: 467 mW (max, 12 ns L version); (5)Low standby power: 0.275 mW (max, L version); (6)2V data retention (L version only); (7)Easy memory expansion with CE and OE features; (8)TTL-compatible inputs and outputs; (9)Automatic power-down when deselected.

Diagrams