TMS320C6701GJC150

Product Summary

The TMS320C6701GJC150 DSPs is the floating-point DSP family in the TMS320C6000ETM DSP platform. The TMS320C6701GJC150 device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the TMS320C6701GJC150 offers cost-effective solutions to high-performance DSP programming challenges. The TMS320C6701GJC150 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The TMS320C6701GJC150 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The TMS320C6701GJC150 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

Parametrics

Absolute maximum ratings: (1)Supply voltage Core, CVdd: 1.71 to 1.89V, the nom value is 1.8V; (2)Supply voltage, I/O, DVdd: 3.14 to 3.46V, the nom is 3.30V; (3)Supply ground, VSS: 0V; (4)High-level input voltage, VIH: 2.0V; (5)Low-level input voltage, VIL: 0.8V; (6)High-level output current, IOH: -12mA; (7)Low-level output current, IOL: 12mA; (8)Case temperature, Default, TC: 0 to 90鈩? (9)Case temperature, A Version, TC: -40 to 105鈩?

Features

Features: (1)Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701; (2)VelociTI: Advanced Very Long Instruction Word (VLIW) C67x CPU Core; (3)1M-Bit On-Chip SRAM; (4)32-Bit External Memory Interface (EMIF); (5)Four-Channel Bootloading: Direct-Memory-Access (DMA) Controller With an Auxiliary Channel; (6)16-Bit Host-Port Interface (HPI); (7)Two Multichannel Buffered Serial Ports (McBSPs); (8)Two 32-Bit General-Purpose Timers; (9)Flexible Phase-Locked-Loop (PLL) Clock Generator; (10)IEEE-1149.1 (JTAG) Boundary-Scan-Compatible; (11)352-Pin Ball Grid Array (BGA) Package (GJC Suffix); (12)0.18-渭m/5-Level Metal Process: CMOS Technology; (13)3.3-V I/Os, 1.8-V Internal (120-, 150-MHz); (14)3.3-V I/Os, 1.9-V Internal (167-MHz Only).

Diagrams

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